NEC Developing Next Generation Vector Supercomputer

on 11 12, 2011

- Aiming for the world’s leading energy-efficient supercomputer -

NEC Corporation (NEC; TSE: 6701) announced today the launch of the development of its next generation of SX Series vector supercomputers.

Vector supercomputers are known to provide a superior sustained performance and efficiency compared to scalar supercomputers (*) in many areas of computational science and engineering, which include large scale data processing at ultra high speeds, such as weather forecast and climatology simulations of the global environment, fluid analysis and research and development of new materials. NEC’s SX Series of vector supercomputers are highly renowned in each of these areas, as illustrated by the sale of more than 1,400 units in many regions all over the world.

NEC’s primary target for the development of the successor of the NEC SX-9 is energy-efficiency for real workload, defined as the optimal ratio of sustained performance on real applications divided by the total cost of ownership (TCO), which in particular includes the cost of electricity. The new machine will be a leader in this regard. Furthermore it will provide a very compact design which ensures highly precise large scale simulations while occupying less space than conventional machines. This new generation of vector computers is scheduled to be available between 2013 and 2014.

Key features of this next generation vector supercomputer are as follows:

1) Top-class energy and space savings
NEC will develop an “all-in-one” CPU, a multi-core vector-processor combining all functions, including compute-cores, memory controllers, network- and I/O-interfaces on one chip. This enables power consumption to be reduced to only one tenth compared to existing systems, and floor space requirements to be reduced to one fifth.

2) Next generation CPU architecture
For the first time the new generation of the SX Series adopts multiple compute-vector-cores on a single chip. NEC will improve parallel processing performance, both on shared-memory and distributed memory paradigms, by enhanced communication latency and bandwidth. The CPU cores will feature twice the number of vector arithmetic units in comparison to existing machines, that way doubling the number of operations that can simultaneously be carried out, utilizing the always existing data-parallelism in applications. NEC will further improve the controllable cache mechanism, the so-called ADB, utilizing the data-locality which is present in almost every application.

3) Improved application performance
A top class CPU core performance of 64 GigaFlops (1 GigaFlops = 1 billion operations per second) is targeted through the adoption of cutting-edge processes that include optimized operation processing and design. A world-leading memory bandwidth of 64 GB/s (GigaBytes per second) available to each core will be implemented. This is the key to achieving high efficiency and consequently high sustained performance on real applications. The road to ExaFlops-computing requires a strong individual processor.

“The new machines will provide a superior sustained performance at a very low power consumption, enabling researchers to quickly and accurately simulate and analyze a wide range of natural phenomena from many scientific fields,” said Mr. Takayuki Sasakura, Vice President at NEC Deutschland.

“NEC plans to provide these machines to universities and research centers both domestically in Japan and internationally, with a focus on Europe. Looking forward, NEC will continue to drive the development of vector supercomputers that help contribute to the realization of ‘an information society friendly to humans and the earth.’”

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